EEPROM flash memories are known in the prior art as large capacitive and multi-functional non-volatile semiconductor memories. In this kind of semiconductor memories, miniaturized circuits with a minimal size of 100 nm or less has been achieved in the memory plane. In order to further increase the memory capacity, it is required to further the miniaturization for increasing a cell number in a unit area. However, it is not easy to further carry forward the miniaturization.
Some approaches have been examined to increase the memory capacity without carrying forward the miniaturization such as, for example, packaging plural memory chips, or forming a three-dimensional memory chip with memory cell arrays stacked above a silicon substrate, and so on. However, conventionally proposed cell array stacking methods are such that planar cell arrays are simply stacked. In these cases, although N times capacity may be obtained by N layers stacking, cell accesses must be independently performed for the respective cell arrays. Therefore, it is not easy to access plural cell arrays at the same time.
As an advanced memory technology of the next generation in the future, there has been proposed a phase change memory which utilizes a phase transition between crystalline and amorphous states of a chalcogenide-based glass material (for example, see Jpn. J. Appl. Phys. Vol. 39 (2000) PP. 6157-6161 Part 1, NO. 11, November 2000 “Submicron Nonvolatile Memory Cell Based on Reversible Phase Transition in Chalcogenide Glasses” Kazuya Nakayama et al). The memory of this type utilizes the fact that a resistance ratio of the amorphous state to the crystalline state of the chalcogenide is as large as 100:1 or more to store therein such different resistance value states as information. This phase change is reversible, and any change can be controlled by adequately designing the way of heating, wherein the heating technique is controllable by the amount of current flowing in this material.
In order to increase the capacity of such a phase change memory, how to integrally form a cell array and a read/write circuit thereof becomes an important technical issue. Additionally, how to design the read/write circuit with the capability to perform high-speed data input/output is also becomes an important technical issue.